Microelectronic Engineering

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  Publication Venue For

  • Barrier engineering for double layer CVD graphene tunnel FETs.  109:117-119. 2013
  • Nanoimprint lithography fabrication of waveguide-integrated optical gratings with inexpensive stamps.  87:1846-1851. 2010
  • Distribution of the contact-potential difference local values over the gate area of MOS structures.  72:165-173. 2004
  • Effects of Ge content in poly-Si1-xGex gate material on the tunneling barrier in PMOS devices.  48:39-42. 1999
  • Modeling the trends in valence-band electron tunneling in NMOSFETs with ultrathin SiO2 and SiO2/Ta2O5 dielectrics with oxide scaling.  48:295-298. 1999
  • Simulation of the drain-current characteristics of MOSFETs with ultrathin oxides in the presence of direct tunneling.  48:101-104. 1999
  • Device physics and simulation of metal/ferroelectric-film/p-type silicon capacitors.  36:95-98. 1997
  • The role of substrate carrier generation in determining the electric field in the oxide of MOS capacitors biased in the Fowler-Norheim tunneling regime.  36:263-266. 1997
  • The onset of the thermal oxidation of silicon from room temperature to 1000°C.  28:109-116. 1995
  • Reliability of III-V devices - The defects that cause the trouble 2012