Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems
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Publication Venue For
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Board-Level Functional Fault Identification Using Streaming Data.
40:1920-1933.
2021
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An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools.
40:1010-1038.
2021
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AccuReD: High Accuracy Training of CNNs on ReRAM/GPU Heterogeneous 3-D Architecture.
40:971-984.
2021
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Improving Multilevel Writes on Vertical 3-D Cross-Point Resistive Memory.
40:762-775.
2021
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Black-Box Test-Cost Reduction Based on Bayesian Network Models.
40:386-399.
2021
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A Hybrid-Grained Remapping Defense Scheme against Hard Failures for Row-Column-NVM
2021
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Correlated Rare Failure Analysis via Asymptotic Probability Evaluation
2021
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Fast Statistical Analysis of Rare Failure Events with Truncated Normal Distribution in High-Dimensional Variation Space
2021
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Formal Synthesis of Adaptive Droplet Routing for MEDA Biochips
2021
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Knowledge Transfer in Board-Level Functional Fault Diagnosis Enabled by Domain Adaptation
2021
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Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation.
39:4971-4984.
2020
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FCDM: A Methodology Based on Sensor Pattern Noise Fingerprinting for Fast Confidence Detection to Adversarial Attacks.
39:4791-4804.
2020
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RED: A ReRAM-Based Efficient Accelerator for Deconvolutional Computation.
39:4736-4747.
2020
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Extending the Lifetime of MEDA Biochips by Selective Sensing on Microelectrodes.
39:3531-3543.
2020
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A Low-Overhead Encoding Scheme to Extend the Lifetime of Nonvolatile Memories.
39:2516-2529.
2020
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Efficient Rare Failure Analysis over Multiple Corners via Correlated Bayesian Inference.
39:2029-2041.
2020
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Fork Path: Batching ORAM Requests to Remove Redundant Memory Accesses.
39:2279-2292.
2020
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Thwarting Replication Attack against Memristor-Based Neuromorphic Computing System.
39:2192-2205.
2020
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SPINBIS: Spintronics-based Bayesian inference system with stochastic computing.
39:789-802.
2020
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An Efficient Fault-Tolerant Valve-Based Microfluidic Routing Fabric for Droplet Barcoding in Single-Cell Analysis.
39:359-372.
2020
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Synthesis of Tamper-Resistant Pin-Constrained Digital Microfluidic Biochips.
39:171-184.
2020
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Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation.
38:1385-1398.
2019
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Exploiting spin-orbit torque devices as reconfigurable logic for circuit obfuscation.
38:57-69.
2019
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Efficient hierarchical performance modeling for analog and mixed-signal circuits via Bayesian co-learning.
37:2986-2998.
2018
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Extending flash lifetime in embedded processors by expanding analog choice.
37:2462-2473.
2018
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TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations.
37:1985-1998.
2018
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Improving Diagnostic Resolution of Failing ICs Through Learning.
37:1288-1297.
2018
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Secure Randomized Checkpointing for Digital Microfluidic Biochips.
37:1119-1132.
2018
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Fine-Grained Aging-Induced Delay Prediction Based on the Monitoring of Run-Time Stress.
37:1064-1075.
2018
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Structural and Functional Test Methods for Micro-Electrode-Dot-Array Digital Microfluidic Biochips.
37:968-981.
2018
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Identifying wafer-level systematic failure patterns via unsupervised learning.
37:832-844.
2018
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Leakage current analysis for diagnosis of bridge defects in power-gating designs.
37:883-895.
2018
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Efficient and Adaptive Error Recovery in a Micro-Electrode-Dot-Array Digital Microfluidic Biochip.
37:601-614.
2018
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Online soft-error vulnerability estimation for memory arrays and logic cores.
37:499-511.
2018
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Guest editorial circuit and system design automation for internet of things.
37:3-6.
2018
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A Branch-&-Bound Test-Access-Mechanism Optimization Method for Multi-$V-{\mathrm{ dd}}$ SoCs.
36:1911-1924.
2017
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A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks.
36:1353-1366.
2017
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Prebond Testing and Test-Path Design for the Silicon Interposer in 2.5-D ICs.
36:1406-1419.
2017
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FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency.
36:1167-1180.
2017
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Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design.
36:1181-1192.
2017
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C-YES: An Efficient Parametric Yield Estimation Approach for Analog and Mixed-Signal Circuits Based on Multicorner-Multiperformance Correlations.
36:899-912.
2017
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Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3-D Small-World Network-on-Chip.
36:719-732.
2017
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Synthesis of Cyberphysical Digital-Microfluidic Biochips for Real-Time Quantitative Analysis.
36:733-746.
2017
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Adaptation of Biochemical Protocols to Handle Technology-Change for Digital Microfluidics.
36:370-383.
2017
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DFM evaluation using IC diagnosis data.
36:463-474.
2017
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Machine Learning for Noise Sensor Placement and Full-Chip Voltage Emergency Detection.
36:421-434.
2017
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Control-Layer Routing and Control-Pin Minimization for Flow-Based Microfluidic Biochips.
36:55-68.
2017
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A Time, Energy, and Area Efficient Domain Wall Memory-Based SPM for Embedded Systems.
35:2008-2017.
2016
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Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors.
35:2148-2152.
2016
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Modeling Random Telegraph Noise as a Randomness Source and its Application in True Random Number Generation.
35:1435-1448.
2016
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Bayesian model fusion: Large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data.
35:1255-1268.
2016
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A novel test method for metallic CNTs in CNFET-Based SRAMs.
35:1192-1205.
2016
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Efficient Board-Level Functional Fault Diagnosis with Missing Syndromes.
35:985-998.
2016
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Efficient Spatial Variation Modeling of Nanoscale Integrated Circuits Via Hidden Markov Tree.
35:971-984.
2016
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On-chip droop-induced circuit delay prediction based on support-vector machines.
35:665-678.
2016
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Wash Optimization and Analysis for Cross-Contamination Removal under Physical Constraints in Flow-Based Microfluidic Biochips.
35:559-572.
2016
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Radiation-induced soft error analysis of STT-MRAM: A device to circuit approach.
35:380-393.
2016
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A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs.
35:309-322.
2016
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Adaptive Board-Level Functional Fault Diagnosis Using Incremental Decision Trees.
35:323-336.
2016
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ExTest Scheduling and Optimization for 2.5D SoCs with Wrapped Tiles.
PP.
2016
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Harvesting Design Knowledge From the Internet: High-Dimensional Performance Tradeoff Modeling for Large-Scale Analog Circuits.
35:23-36.
2016
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RRAM-Based Analog Approximate Computing.
34:1905-1917.
2015
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Robust Optimization of Test-Access Architectures under Realistic Scenarios.
34:1873-1884.
2015
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Test-cost modeling and optimal test-flow selection of 3-D-stacked ICs.
34:1523-1536.
2015
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Fast Statistical Analysis of Rare Circuit Failure Events via Scaled-Sigma Sampling for High-Dimensional Variation Space.
34:1096-1109.
2015
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Information-theoretic syndrome evaluation, statistical root-cause analysis, and correlation-based feature selection for guiding board-level fault diagnosis.
34:1014-1026.
2015
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Time-Division Multiplexing for Testing DVFS-Based SoCs.
34:668-681.
2015
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Accurate predictions of process-execution time and process status based on support-vector regression for enterprise information systems.
34:354-366.
2015
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Efficient transient analysis of power delivery network with clock/power gating by sparse approximation.
34:409-421.
2015
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A novel analog physical synthesis methodology integrating existent design expertise.
34:199-212.
2015
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Interconnect testing and test-path scheduling for interposer-based 2.5-D ICs.
34:136-149.
2015
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Reuse-based optimization for prebond and post-bond testing of 3-D-stacked ICs.
34:122-135.
2015
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PS3-RAM: A fast portable and scalable statistical STT-RAM reliability/energy analysis method.
33:1644-1656.
2014
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Testing of flow-based microfluidic biochips: Fault modeling, test generation, and experimental demonstration.
33:1463-1475.
2014
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Retiming for delay recovery after DfT insertion on interdie paths in 3-D ICs.
33:464-475.
2014
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Biochip synthesis and dynamic error recovery for sample preparation using digital microfluidics.
33:183-196.
2014
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Board-level functional fault diagnosis using multikernel support vector machines and incremental learning.
33:279-290.
2014
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Biochemistry synthesis on a cyberphysical digital microfluidics platform under completion-time uncertainties in fluidic operations.
33:903-916.
2014
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Built-in self-test, diagnosis, and repair of multimode power switches.
33:1231-1244.
2014
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Contactless pre-bond TSV test and diagnosis using ring oscillators and multiple voltage levels.
33:774-785.
2014
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Multiple-population moment estimation: Exploiting interpopulation correlation for efficient moment estimation in analog/mixed-signal validation.
33:961-974.
2014
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On-chip sample preparation for multiple targets using digital microfluidics.
33:1131-1144.
2014
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Scan-based testing of post-bond silicon interposer interconnects in 2.5-D ICs.
33:1410-1423.
2014
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Test-delivery optimization in manycore SOCs.
33:1067-1080.
2014
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Real-time error recovery in cyberphysical digital-microfluidic biochips using a compact dictionary.
32:1839-1852.
2013
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Generation of effective 1-detect TDF patterns for detecting small-delay defects.
32:1583-1594.
2013
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Design of pin-constrained general-purpose Digital microfluidic biochips.
32:1307-1320.
2013
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Detection, diagnosis, and recovery from Clock-Domain Crossing failures in multiclock SoCs.
32:1395-1408.
2013
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Efficient spatial pattern analysis for variation decomposition via robust sparse regression.
32:1072-1085.
2013
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Board-level functional fault diagnosis using artificial neural networks, support-vector machines, and weighted-majority voting.
32:723-736.
2013
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Pre-bond probing of through-silicon vias in 3-D stacked ICs.
32:547-558.
2013
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Counter-based output selection for test response compaction.
32:152-164.
2013
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Error recovery in cyberphysical digital microfluidic biochips.
32:59-72.
2013
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Efficient SRAM failure rate prediction via Gibbs sampling.
31:1831-1844.
2012
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A reagent-saving mixing algorithm for preparing multiple-target biochemical samples using digital microfluidics.
31:1656-1669.
2012
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Test schedule optimization for multicore SoCs: Handling dynamic voltage scaling and multiple voltage islands.
31:1754-1766.
2012
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Diagnosis of board-level functional failures under uncertainty using Dempster-Shafer theory.
31:1586-1599.
2012
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Cross-contamination avoidance for droplet routing in digital microfluidic biochips.
31:817-830.
2012
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Reproduction and detection of board-level functional failure.
31:630-643.
2012
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Simultaneous optimization of droplet routing and control-pin mapping to electrodes in digital microfluidic biochips.
31:242-254.
2012
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Virtual probe: A statistical framework for low-cost silicon characterization of nanoscale integrated circuits.
30:1814-1827.
2011
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MVP: Minimum-violations partitioning for reducing capture power in at-speed delay-fault testing.
30:1762-1767.
2011
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Test-architecture optimization and test scheduling for TSV-based 3-D stacked ICs.
30:1705-1718.
2011
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Broadcast electrode-addressing and scheduling methods for pin-constrained digital microfluidic biochips.
30:986-999.
2011
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Generation of compact stuck-at test sets targeting unmodeled defects.
30:787-791.
2011
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Finding deterministic solution from underdetermined equation: Large-scale performance variability modeling of analog/RF circuits.
29:1661-1668.
2010
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Optimization of dilution and mixing of biochemical samples using digital microfluidic biochips.
29:1696-1708.
2010
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Gate-sizing-based single Vdd test for bridge defects in multivoltage designs.
29:1409-1421.
2010
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Design tools for digital microfluidic biochips: Toward functional diversification and more than Moore.
29:1001-1017.
2010
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Test-pattern selection for screening small-delay defects in very-deep submicrometer integrated circuits.
29:760-773.
2010
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Defect-tolerant design and optimization of a digital microfluidic biochip for protein crystallization.
29:552-565.
2010
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Statistical modeling with the PSP MOSFET model.
29:599-609.
2010
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Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip.
28:1251-1264.
2009
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Regular analog/RF integrated circuits design using optimization with recourse including ellipsoidal uncertainty.
28:623-637.
2009
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Deviation-Based LFSR Reseeding for Test-Data Compression.
28:259-271.
2009
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Deviation-based LFSR reseeding for test-data compression.
28:259-271.
2009
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Integrated LFSR reseeding, test-access optimization, and test scheduling for core-based system-on-chip.
28:1251-1264.
2009
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Regular analog/RF integrated circuits design using optimization with recourse including ellipsoidal uncertainty.
28:623-637.
2009
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Test-length and TAM optimization for wafer-level reduced pin-count testing of core-based SoCs.
28:111-120.
2009
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A droplet-manipulation method for achieving high-throughput in cross-referencing-based digital microfluidic biochips.
27:1905-1917.
2008
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A reconfigurable scan architecture with weighted scan-enable signals for deterministic BIST.
27:999-1012.
2008
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Cycle-accurate test power modeling and its application to SoC test architecture design and scheduling.
27:973-977.
2008
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Quadratic statistical MAX approximation for parametric yield estimation of analog/RF integrated circuits.
27:831-842.
2008
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Test-quality/cost optimization using output-deviation-based reordering of test patterns.
27:352-365.
2008
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Test wrapper design and optimization under power constraints for embedded cores with multiple clock domains.
26:1539-1547.
2007
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Asymptotic probability extraction for nonnormal performance distributions.
26:16-37.
2007
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Robust analog/RF circuit design with projection-based performance modeling.
26:2-15.
2007
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Defect tolerance based on graceful degradation and dynamic reconfiguration for digital microfluidics-based biochips.
25:2944-2953.
2006
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Identifying the source of BW failures in high-frequency linear analog circuits based on S-parameter measurements.
25:2594-2605.
2006
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Thermal-safe test scheduling for core-based system-on-chip integrated circuits.
25:2502-2511.
2006
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems: Guest editorial.
25:209-210.
2006
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Microfluidics-based biochips: Technology issues, implementation platforms, and design-automation challenges.
25:211-223.
2006
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A unified approach for fault tolerance and dynamic power management in fixed-priority real-time embedded systems.
25:111-125.
2006
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An efficient 3-D spectral-element method for schrödinger equation in nanodevice simulation.
24:1848-1858.
2005
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Test Planning for modular testing of hierarchical SOCs.
24:435-447.
2005
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Identification of error-capturing scan cells in scan-BIST with applications to system-on-chip.
23:1447-1459.
2004
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Network flow techniques for dynamic voltage scaling in hard real-time systems.
23:1385-1398.
2004
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Test set embedding for deterministic BIST using a reconfigurable interconnection network.
23:1289-1305.
2004
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The spectral grid method: A novel fast Schrödinger-equation solver for semiconductor nanodevice simulation.
23:1200-1208.
2004
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Energy-conscious, deterministic I/O device scheduling in hard real-time systems.
22:847-858.
2003
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Efficient test access mechanism optimization for system-on-chip.
22:635-643.
2003
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Failing vector identification based on overlapping intervals of test vectors in a scan-BIST environment.
22:593-604.
2003
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A unified approach to reduce SOC test data volume, scan power and testing time.
22:352-362.
2003
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Synthesis of single-output space compactors for scan-based sequential circuits.
21:1171-1179.
2002
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System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints.
21:1088-1094.
2002
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Test data compression and decompression based on internal scan chains and Golomb coding.
21:715-722.
2002
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Low-power scan testing and test data compression for system-on-a-chip.
21:597-604.
2002
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Scheduling of microfluidic operations for reconfigurable two-dimensional electrowetting arrays.
20:1463-1468.
2001
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System-on-a-chip test-data compression and decompression architectures based on Golomb codes.
20:355-368.
2001
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Test scheduling for core-based systems using mixed-integer linear programming.
19:1163-1174.
2000
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Design of built-in test generator circuits using width compression.
17:1044-1051.
1998
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Zero-aliasing space compaction using linear compactors with bounded overhead.
17:452-457.
1998
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On the quality of accumulator-based compaction of test responses.
16:916-922.
1997
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Test response compaction using multiplexed parity trees.
15:1399-1408.
1996
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A Parasitics Extraction and Network Reduction Algorithm for Analog VLSI.
10:145-149.
1991
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TwoDimensional Process Simulation Using Verified Phenomenological Models.
10:643-651.
1991
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Two-Dimensional Impurity Profiling with Emission Computed Tomography Techniques.
8:323-335.
1989
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Fault diagnosis for leakage and blockage defects in flow-based microfluidic biochips
2016
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Design and optimization of a cyberphysical digital-microfluidic biochip for the polymerase chain reaction
2015
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Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations
2008