Proceedings Design Automation Conference
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Publication Venue For
- Architecting dynamic power management to be formally verifiable 2014
- Demand-driven mixture preparation and droplet streaming using digital microfluidic biochips 2014
- Design of cyberphysical digital microfluidic biochips under completion-time uncertainties in fluidic operations 2013
- On effective and efficient in-field TSV repair for stacked 3D ICs 2013
- Design of pin-constrained general-purpose digital microfluidic biochips. 18-25. 2012
- TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation. 1024-1030. 2012
- Joint DAC/IWBDA special session design and synthesis of biological circuits. 114-115. 2011
- Synchronization of washing operations with droplet routing for cross-contamination avoidance in digital microfluidic biochips. 635-640. 2010
- Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips. 173-178. 2008
- Engineering synthetic killer circuits in bacteria. 636-637. 2007
- Integrated droplet routing in the synthesis of microfluidic biochips. 948-953. 2007
- SOC test architecture optimization for signal integrity faults on core-external interconnects. 676-681. 2007
- Automated design of pin-constrained digital microfluidic arrays for lab-on-a-chip applications*. 925-930. 2006
- Design automation for DNA self-assembled nanostructures. 919-924. 2006
- Multi-frequency wrapper design and optimization for embedded cores under average power constraints. 123-128. 2005
- Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips. 825-830. 2005
- Energy-aware deterministic fault tolerance in distributed real-time embedded systems. 550-555. 2004
- Test cost reduction for SOCs using virtual TAMs and lagrange multipliers. 738-743. 2003
- Reduction of SOC test data volume, scan power and testing time using alternating run-length codes. 673-678. 2002
- Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs. 685-690. 2002
- Combining low-power scan testing and test data compression for system-on-a-chip. 166-169. 2001
- Design of system-on-a-chip test access architectures under place-and-route and power constraints. 432-437. 2000
- DFBT: a design-for-testability method based on balance testing. 351-357. 1994
- Lattice: An ADC/DAC-less ReRAM-based processing-in-memory architecture for accelerating deep convolution neural networks 2020
- ReSiPE: ReRAM-based single-spiking processing-in-memory engine 2020
- SparseTrain: Exploiting dataflow sparsity for efficient convolutional neural networks training 2020
- Adaptive granularity encoding for energy-efficient non-volatile main memory 2019
- ESLAM: An energy-efficient accelerator for real-time ORB-SLAM on FPGA platform 2019
- MobiEye: An efficient cloud-based video detection system for real-time mobile applications 2019
- Correlated Rare Failure Analysis via Asymptotic Probability Evaluation 2017
- Efficient Hierarchical Performance Modeling for Integrated Circuits via Bayesian Co-Learning 2017
- Fault-Tolerant Training with On-Line Fault Detection for RRAM-Based Neural Computing Systems 2017
- Group Scissor: Scaling Neuromorphic Computing Design to Large Neural Networks 2017
- Rescuing Memristor-based Neuromorphic Design with High Defects 2017
- A new learning method for inference accuracy, core occupation, and performance co-optimization on TrueNorth chip 2016
- AOS: Adaptive overwrite scheme for energy-efficient MLC STT-RAM cache 2016
- Correlated Bayesian Model Fusion: Efficient performance modeling of large-scale tunable analog/RF integrated circuits 2016
- Efficient performance modeling of analog integrated circuits via kernel density based sparse regression 2016
- Efficient performance modeling via Dual-Prior Bayesian Model Fusion for analog and mixed-signal circuits 2016
- High-level synthesis for micro-electrode-dot-array digital microfluidic biochips 2016
- MORPh: Mobile OLED-friendly recording and playback system for low power video streaming 2016
- NVSim-VXs : An improved NVSim for variation aware STT-RAM simulation 2016
- TEMP: Thread batch enabled memory partitioning for GPU 2016
- Area and performance co-optimization for domain wall memory in application-specific embedded systems 2015
- Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits 2015
- A spiking neuromorphic design with resistive crossbar 2015
- An EDA framework for large scale hybrid neuromorphic computing systems 2015
- Cloning your mind: Security challenges in cognitive system designs and their solutions 2015
- DaTuM: Dynamic tone mapping technique for OLED display power saving based on video classification 2015
- FlexLevel: A novel NAND flash storage system design for LDPC latency reduction 2015
- Jump test for metallic CNTs in CNFET-based SRAM 2015
- MTunes: Efficient post-silicon tuning of mixed-signal/RF integrated circuits based on Markov decision process 2015
- RENO: A high-efficient reconfigurable neuromorphic computing accelerator design 2015
- VWS: A versatile warp scheduler for exploring diverse cache localities of GPGPU applications 2015
- Vortex: Variation-aware training for memristor X-bar 2015
- A new field-assisted access scheme of STT-RAM with self-reference capability 2014
- BMF-BD: Bayesian model fusion on bernoulli distribution for efficient yield estimation of integrated circuits 2014
- Computer-aided design of machine learning algorithm: Training fixed-point classifier for on-chip low-power implementation 2014
- Demystifying energy usage in smartphones 2014
- Ebutton: A wearable computer for health monitoring and personal assistance 2014
- Exploration of GPGPU register file architecture using domain-wall-shift- write based racetrack memory 2014
- State-restrict MLC stt-ram designs for high-reliable high-performance memory system 2014
- Automatic clustering of wafer spatial signatures 2013
- Bayesian model fusion: Large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data 2013
- Cross-layer racetrack memory design for ultra high density and low power consumption 2013
- Efficient moment estimation with extremely small sample size via bayesian inference for analog/mixed-signal validation 2013
- Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine 2013
- An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoring 2012
- Hardware realization of BSB recall function using memristor crossbar arrays 2012
- PS3-RAM: A fast portable and scalable statistical STT-RAM reliability analysis method 2012
- Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devices 2012
- Statistical design and optimization for adaptive post-silicon tuning of MEMS filters 2012
- Statistical memristor modeling and case study in neuromorphic computing 2012
- Rethinking memory redundancy: Optimal bit cell repair for maximum-information storage 2011
- Efficient SRAM failure rate prediction via Gibbs sampling 2011
- Efficient incremental analysis of on-chip power grid via sparse approximation 2011
- Bayesian Virtual Probe: Minimizing variation characterizationcost for nanoscale IC technologies via Bayesian inference 2010
- Impact of process variations on emerging memristor 2010
- Toward efficient large-scale performance modeling of integrated circuits via multi-mode/multi-corner sparse regression 2010
- Efficient design-specific worst-case corner extraction for integrated circuits 2009
- Finding deterministic solution from underdetermined equation: Large-scale performance modeling by least angle regression 2009
- Improving STT MRAM storage density through smaller-than-worst-case transistor sizing 2009
- SRAM parametric failure analysis 2009
- Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement 2008
- Statistical regression for efficient high-dimensional modeling of analog and mixed-signal performance variations 2008
- Efficient parametric yield extraction for multiple correlated non-normal performance distributions of analog/RF circuits 2007
- Parameterized macromodeling for analog system-level design exploration 2007
- Architecture-aware FPGA placement using metric embedding 2006
- Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions 2006
- OPERA: Optimization with ellipsoidal uncertainty for robust analog IC design 2005
- Correlation-aware statistical timing analysis with non-gaussian delay distributions 2005
- STAC: Statistical timing analysis with correlation 2004
- A frequency relaxation approach for analog/RF system-level simulation 2004
- Analog and RF circuit macromodels for system-level analysis 2003
- DRG-Cache: A data retention gated-ground cache for low power 2002