Proceedings Design, Automation and Test in Europe, Date
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Publication Venue For
- Nostradamus: Low-cost hardware-only error detection for processor cores 2014
- Fault detection, real-time error recovery, and experimental demonstration for digital microfluidic biochips. 559-564. 2013
- Architectures for online error detection and recovery in multicore processors. 533-538. 2011
- A special-purpose compiler for look-up table and code generation for function evaluation. 1130-1135. 2010
- Circuit-level modeling for concurrent testing of operational defects due to gate oxide breakdown. I:300-305. 2005
- An Efficient Programming Framework for Memristor-based Neuromorphic Computing 2021
- Efficient AUTOSAR-Compliant CAN-FD Frame Packing with Observed Optimality 2021
- Fault-Criticality Assessment for AI Accelerators using Graph Convolutional Networks 2021
- Formal Synthesis of Adaptive Droplet Routing for MEDA Biochips 2021
- Marvel: A Vertical Resistive Accelerator for Low-Power Deep Learning Inference in Monolithic 3D 2021
- RAISE: A Resistive Accelerator for Subject-Independent EEG Signal Classification 2021
- A fast spatial variation modeling algorithm for efficient test cost reduction of analog/RF circuits 2015
- Efficient bit error rate estimation for high-speed link by Bayesian model fusion 2015
- Fast deployment of alternate analog test using Bayesian model fusion 2015
- Giant spin hall effect (GSHE) logic design for low power application 2015
- Optimization of quantum computer architecture using a resource-performance simulator 2015
- Spiking neural network with RRAM: Can we use it for real-world application? 2015
- Accelerating graph computation with racetrack memory and pointer-assisted graph representation 2014
- Energy efficient neural networks for big data analytics 2014
- ICE: Inline calibration for memristor crossbar-based computing engine 2014
- Nostradamus: Low-cost hardware-only error detection for processor cores 2014
- Cache coherence enabled adaptive refresh for volatile STT-RAM 2013
- DA-RAID-5: A disturb aware data protection technique for NAND flash storage systems 2013
- Low cost power failure protection for MLC NAND flash storage systems with PRAM/DRAM hybrid buffer 2013
- STT-RAM designs supporting dual-port accesses 2013
- Architecting a common-source-line array for bipolar non-volatile memory devices 2012
- Asymmetry of MTJ switching and its implication to STT-RAM designs 2012
- Spintronic memristor based temperature sensor design with CMOS current reference 2012
- 3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers 2011
- A nondestructive self-reference scheme for spin-transfer torque random access memory (STT-RAM) 2010
- Compact model of memristors and its application in computing systems 2010
- Spintronic memristor devices and application 2010
- An overview of non-volatile memory technology and the implication for tools and architectures 2009
- Modeling interconnect variability using efficient parametric model order reduction 2005
- Noise macromodel for radio frequency integrated circuits 2003
- Noise macromodel for radio frequency integrated circuits 2003
- Model reduction in the time-domain using Laguerre polynomials and Krylov methods 2002