Efficient sorting using register and caches

Published

Journal Article

© 2002, Association for Computing Machinery. All rights reserved. Modern computer systems have increasingly complex memory systems. Common machine models for algorithm analysis do not reflect many of the features of these systems, e.g., large register sets, lockup-free caches, cache hierarchies, associativity, cache line fetching, and streaming behavior. Inadequate models lead to poor algorithmic choices and an incomplete understanding of algorithm behavior on real machines. A key step toward developing better models is to quantify the performance effects of features not reflected in the models. This paper explores the effect of memory system features on sorting performance. We introduce a new cache-conscious sorting algorithm, R-MERGE, which achieves better performance in practice over algorithms that are superior in the theoretical models. R-MERGE is designed to minimize memory stall cycles rather than cache misses by considering features common to many system designs.

Full Text

Duke Authors

Cited Authors

  • Wickremesinghe, R; Arge, L; Chase, JS; Vitter, JS

Published Date

  • January 1, 2002

Published In

Volume / Issue

  • 7 /

International Standard Serial Number (ISSN)

  • 1084-6654

Digital Object Identifier (DOI)

  • 10.1145/944618.944627

Citation Source

  • Scopus