Current saturation in submicrometer graphene transistors with thin gate dielectric: experiment, simulation, and theory.

Published

Journal Article

Recently, graphene field-effect transistors (FET) with cutoff frequencies (f(T)) between 100 and 300 GHz have been reported; however, the devices showed very weak drain current saturation, leading to an undesirably high output conductance (g(ds)= dI(ds)/dV(ds)). A crucial figure-of-merit for analog/RF transistors is the intrinsic voltage gain (g(m)/g(ds)) which requires both high g(m) (primary component of f(T)) and low g(ds). Obtaining current saturation has become one of the key challenges in graphene device design. In this work, we study theoretically the influence of the dielectric thickness on the output characteristics of graphene FETs by using a surface-potential-based device model. We also experimentally demonstrate that by employing a very thin gate dielectric (equivalent oxide thickness less than 2 nm), full drain current saturation can be obtained for large-scale chemical vapor deposition graphene FETs with short channels. In addition to showing intrinsic voltage gain (as high as 34) that is comparable to commercial semiconductor FETs with bandgaps, we also demonstrate high frequency AC voltage gain and S21 power gain from s-parameter measurements.

Full Text

Duke Authors

Cited Authors

  • Han, S-J; Reddy, D; Carpenter, GD; Franklin, AD; Jenkins, KA

Published Date

  • June 2012

Published In

Volume / Issue

  • 6 / 6

Start / End Page

  • 5220 - 5226

PubMed ID

  • 22582702

Pubmed Central ID

  • 22582702

Electronic International Standard Serial Number (EISSN)

  • 1936-086X

International Standard Serial Number (ISSN)

  • 1936-0851

Digital Object Identifier (DOI)

  • 10.1021/nn300978c

Language

  • eng