Real-time QRD-based beamforming on an FPGA platform

Published

Conference Paper

This paper describes the architecture, design flow and verification process for the FPGA implementation of a real-time beamformer. One of the challenges in realizing this class of processing is in the implementation of the linear algebra operations required in forming the least-squares solution to the Normal equations. We describe the FPGA realization of a flexible QRD-based approach to this problem in which the system parameters (row and column dimensions) can be supplied to the beamformer module at run-time. The design and FPGA implementation of the beamformer architecture and verification framework is described along with implementation considerations for Xilinx Virtex™-4 family of FPGAs. A model-based FPGA design flow called System Generator™ [4], based on the The Mathworks Siniulink®visual programming environment, was used exclusively to generate the implementation. The use of this tool chain for hardware verification is discussed. The FPGA resource utilization and performance of the QRD processor is reported.

Full Text

Duke Authors

Cited Authors

  • Dick, C; Harris, F; Pajic, M; Vuletic, D

Published Date

  • December 1, 2006

Published In

Start / End Page

  • 1200 - 1204

International Standard Serial Number (ISSN)

  • 1058-6393

International Standard Book Number 10 (ISBN-10)

  • 1424407850

International Standard Book Number 13 (ISBN-13)

  • 9781424407859

Digital Object Identifier (DOI)

  • 10.1109/ACSSC.2006.354945

Citation Source

  • Scopus