Time-Division Multiplexing for Testing DVFS-Based SoCs

Published

Journal Article

© 1982-2012 IEEE. Dynamic voltage-frequency scaling (DVFS) is used in system-on-chips (SoCs) for power management, but it increases test time because every core must be tested at multiple voltage settings. In addition, testing at lower power supply voltage settings increases the length of each test due to the corresponding reduction in frequencies that can be used for scan shift operations. Existing test scheduling techniques do not consider test applications at multiple voltage settings, therefore they are not effective for reducing test time for DVFS-based SoCs. We propose a time-division multiplexing (TDM) architecture, which uses the highest available frequency for shifting test data into the SoC and then distributes the test data into multiple cores using lower shift frequencies. TDM is accompanied by three test scheduling methods, which are suitable for different scenarios: 1) an integer linear programming-based formulation that offers optimal results for SOCs of moderate size; 2) a greedy approach that provides good results with very short run time even for very large SoCs; and 3) a rectangle-packing approach combined with simulated-annealing that offers a trade-off between run time and test-time reduction for all SoCs. Experimental results on two industrial SoCs highlight the effectiveness of TDM and the associated scheduling methods.

Full Text

Duke Authors

Cited Authors

  • Vartziotis, F; Kavousianos, X; Chakrabarty, K; Jain, A; Parekhji, R

Published Date

  • April 1, 2015

Published In

Volume / Issue

  • 34 / 4

Start / End Page

  • 668 - 681

International Standard Serial Number (ISSN)

  • 0278-0070

Digital Object Identifier (DOI)

  • 10.1109/TCAD.2015.2394462

Citation Source

  • Scopus