Test-cost modeling and optimal test-flow selection of 3-D-stacked ICs

Published

Journal Article

© 2015 IEEE. Three-dimensional (3-D) integration is an attractive technology platform for next-generation ICs. Despite the benefits offered by 3-D integration, test cost remains a major concern, and analysis and tools are needed to understand test flows and minimize test cost. We propose a generic cost model to account for various test costs involved in 3-D integration and present a formal representation of the solution space to minimize the overall cost. We present an algorithm based on A∗ - a best-first search technique - to obtain an optimal solution. An approximation algorithm with provable bounds on optimality is proposed to further reduce the search space. In contrast to prior work, which is based on explicit enumeration of test flows, we adopt a formal optimization approach, which allows us to select an effective test flow by systematically exploring an exponentially large number of candidate test flows. Experimental results highlight the effectiveness of the proposed method. Adopting a formal approach to solving the cost-minimization problem provides useful insights that cannot be derived via selective enumeration of a smaller number of candidate test flows.

Full Text

Duke Authors

Cited Authors

  • Agrawal, M; Chakrabarty, K

Published Date

  • September 1, 2015

Published In

Volume / Issue

  • 34 / 9

Start / End Page

  • 1523 - 1536

International Standard Serial Number (ISSN)

  • 0278-0070

Digital Object Identifier (DOI)

  • 10.1109/TCAD.2015.2419227

Citation Source

  • Scopus