Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy
Conference Paper
In this work, we provide energy-efficient architectural support for floating point accuracy. For each floating point addition performed, we "recycle" that operation's rounding error. We make this error architecturally visible such that it can be used, whenever desired, by software. We also design a compiler pass that allows software to automatically use this feature. Experimental results on physical hardware show that software that exploits architecturally recycled error bits can (a) achieve accuracy comparable to a 64-bit FPU with performance and energy that are comparable to a 32-bit FPU, and (b) achieve accuracy comparable to an all-software scheme for 128-bit accuracy with far better performance and energy usage.
Full Text
Duke Authors
Cited Authors
- Nathan, R; Anthonio, B; Lu, SL; Naeimi, H; Sorin, DJ; Sun, X
Published Date
- January 16, 2014
Published In
Volume / Issue
- 2015-January / January
Start / End Page
- 117 - 127
Electronic International Standard Serial Number (EISSN)
- 2167-4337
International Standard Serial Number (ISSN)
- 2167-4329
Digital Object Identifier (DOI)
- 10.1109/SC.2014.15
Citation Source
- Scopus