Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy
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Nathan, R; Anthonio, B; Lu, SL; Naeimi, H; Sorin, DJ; Sun, X
Published in: International Conference for High Performance Computing, Networking, Storage and Analysis, SC
January 16, 2014
In this work, we provide energy-efficient architectural support for floating point accuracy. For each floating point addition performed, we "recycle" that operation's rounding error. We make this error architecturally visible such that it can be used, whenever desired, by software. We also design a compiler pass that allows software to automatically use this feature. Experimental results on physical hardware show that software that exploits architecturally recycled error bits can (a) achieve accuracy comparable to a 64-bit FPU with performance and energy that are comparable to a 32-bit FPU, and (b) achieve accuracy comparable to an all-software scheme for 128-bit accuracy with far better performance and energy usage.
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Published In
International Conference for High Performance Computing, Networking, Storage and Analysis, SC
DOI
EISSN
2167-4337
ISSN
2167-4329
Publication Date
January 16, 2014
Volume
2015-January
Issue
January
Start / End Page
117 / 127
Citation
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Chicago
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Nathan, R., Anthonio, B., Lu, S. L., Naeimi, H., Sorin, D. J., & Sun, X. (2014). Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy. In International Conference for High Performance Computing, Networking, Storage and Analysis, SC (Vol. 2015-January, pp. 117–127). https://doi.org/10.1109/SC.2014.15
Nathan, R., B. Anthonio, S. L. Lu, H. Naeimi, D. J. Sorin, and X. Sun. “Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy.” In International Conference for High Performance Computing, Networking, Storage and Analysis, SC, 2015-January:117–27, 2014. https://doi.org/10.1109/SC.2014.15.
Nathan R, Anthonio B, Lu SL, Naeimi H, Sorin DJ, Sun X. Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy. In: International Conference for High Performance Computing, Networking, Storage and Analysis, SC. 2014. p. 117–27.
Nathan, R., et al. “Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy.” International Conference for High Performance Computing, Networking, Storage and Analysis, SC, vol. 2015-January, no. January, 2014, pp. 117–27. Scopus, doi:10.1109/SC.2014.15.
Nathan R, Anthonio B, Lu SL, Naeimi H, Sorin DJ, Sun X. Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy. International Conference for High Performance Computing, Networking, Storage and Analysis, SC. 2014. p. 117–127.
Published In
International Conference for High Performance Computing, Networking, Storage and Analysis, SC
DOI
EISSN
2167-4337
ISSN
2167-4329
Publication Date
January 16, 2014
Volume
2015-January
Issue
January
Start / End Page
117 / 127