Scaling and packing on a chip multiprocessor

Published

Conference Paper

Power management is critical in server and high-performance computing environments as well as in mobile computing. Many mechanisms have been developed over recent years to support a wide a variety of power management techniques. In particular, general purpose microprocessors now support dynamically modifying the power-performance state through voltage and frequency changes. This development spawned a very important area of this research in dynamic voltage and frequency scaling (DVFS). On the other hand, in a multiprocessor environment one can perform power management by offlining and idling processors when computational demand is low in a technique called CPU packing. This paper examines the effect of combining voltage and frequency scaling and CPU packing in a multiprocessor. Furthermore, it examines DVFS on a chip multiprocessor in which multiple processor cores are placed on a single die. This paper shows that in general one should use DVFS first, then CPU packing. Furthermore, we find that the effectiveness of CPU packing is application-dependent: commercial workloads (e.g. Apache) with periods of low utilization can reduce power by as much as 19% via packing, while the improvement to HPC workloads ranges from small to negligible. © 2007 IEEE.

Full Text

Duke Authors

Cited Authors

  • Freeh, VW; Bletsch, TK; Rawson, FL

Published Date

  • September 24, 2007

Published In

  • Proceedings 21st International Parallel and Distributed Processing Symposium, Ipdps 2007; Abstracts and Cd Rom

International Standard Book Number 10 (ISBN-10)

  • 1424409101

International Standard Book Number 13 (ISBN-13)

  • 9781424409105

Digital Object Identifier (DOI)

  • 10.1109/IPDPS.2007.370539

Citation Source

  • Scopus