Adagio: Making DVS practical for complex HPC applications

Published

Conference Paper

Power and energy are first-order design constraints in high performance computing. Current research using dynamic voltage scaling (DVS) relies on trading increased execution time for energy savings, which is unacceptable for most high performance computing applications. We present Adagio, a novel runtime system that makes DVS practical for complex, real-world scientific applications by incurring only negligible delay while achieving signifi-cant energy savings. Adagio improves and extends previous stateof-the-art algorithms by combining the lessons learned from static energy-reducing CPU scheduling with a novel runtime mechanism for slack prediction. We present results using Adagio for two realworld programs, UMT2K and ParaDiS, along with the NAS Parallel Benchmark suite. While requiring no modification to the application source code, Adagio provides total system energy savings of 8% and 20% for UMT2K and ParaDiS, respectively, with less than 1% increase in execution time. Copyright 2009 ACM.

Full Text

Duke Authors

Cited Authors

  • Rountree, B; Lowenthal, DK; De Supinski, BR; Schulz, M; Freeh, VW; Bletsch, T

Published Date

  • November 24, 2009

Published In

  • Proceedings of the International Conference on Supercomputing

Start / End Page

  • 460 - 469

International Standard Book Number 13 (ISBN-13)

  • 9781605584980

Digital Object Identifier (DOI)

  • 10.1145/1542275.1542340

Citation Source

  • Scopus