Efficient sorting using registers and caches


Journal Article

Modern computer systems have increasingly complex memory systems. Common machine models for algorithm analysis do not reflect many of the features of these systems, e.g., large register sets, lockup-free caches, cache hierarchies, associativity, cache line fetching, and streaming behavior. Inadequate models lead to poor algorithmic choices and an incomplete understanding of algorithm behavior on real machines. A key step toward developing better models is to quantify the performance effects of features not reflected in the models. This paper explores the effect of memory system features on sorting performance. We introduce a new cache-conscious sorting algorithm, R-MERGE, which achieves better performance in practice over algorithms that are theoretically superior under the models. R-MERGE is designed to minimize memory stall cycles rather than cache misses, considering features common to many system designs. © Springer-Verlag Berlin Heidelberg 2001.

Full Text

Duke Authors

Cited Authors

  • Arge, L; Chase, J; Vitter, JS; Wickremesinghe, R

Published Date

  • January 1, 2001

Published In

Volume / Issue

  • 1982 LNCS /

Start / End Page

  • 51 - 62

Electronic International Standard Serial Number (EISSN)

  • 1611-3349

International Standard Serial Number (ISSN)

  • 0302-9743

Digital Object Identifier (DOI)

  • 10.1007/3-540-44691-5_5

Citation Source

  • Scopus