Design-for-test and test optimization techniques for TSV-based 3D stacked ICs



© Springer International Publishing Switzerland 2014. This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

Full Text

Duke Authors

Cited Authors

  • Noia, B; Chakrabarty, K

Published Date

  • January 1, 2014

Start / End Page

  • 1 - 245

International Standard Book Number 13 (ISBN-13)

  • 9783319023779

Digital Object Identifier (DOI)

  • 10.1007/978-3-319-02378-6

Citation Source

  • Scopus