Decoupling Loads for Nano-Instruction Set Computers

Other Article

We propose an ISA extension that decouples the data access and register write operations in a load instruction. We describe system and hardware support for decoupled loads. Furthermore, we show how compilers can generate better static instruction schedules by hoisting a decoupled load's data access above may-alias stores and branches. We find that decoupled loads improve performance with geometric mean speedups of 8.4%.

Full Text

Duke Authors

Cited Authors

  • Huang, Z; Hilton, AD; Lee, BC

Published Date

  • August 24, 2016

Published In

  • Proceedings 2016 43rd International Symposium on Computer Architecture, Isca 2016

Start / End Page

  • 406 - 417

International Standard Book Number 13 (ISBN-13)

  • 9781467389471

Digital Object Identifier (DOI)

  • 10.1109/ISCA.2016.43

Citation Source

  • Scopus