ExTest Scheduling and Optimization for 2.5D SoCs with Wrapped Tiles

Published

Journal Article

© 2016 IEEE. Interposer-based 2.5D integrated circuits (ICs) enable high-density interconnects, but introduce new challenges for the testing of a system-on-chip (SoC) die on an interposer. This paper presents two efficient ExTest scheduling strategies that implements interconnect testing between tiles inside an SoC die while satisfying the practical constraint that the number of required test pins cannot exceed the number of available pins at the chip level. These strategies target two different ways in which SoC dies are wrapped in 2.5D ICs. The first scheduling approach is aimed at an extremely large SoC in which the wrapper design requires concurrent testing of the interconnects driving the tile under test. The second scheduling approach is applicable to more general wrapper designs that provide more flexibility in terms of the manner in which these interconnects can be tested. In both test strategies, the tiles in the SoC die are divided into groups based on the manner in which they are interconnected. In order to minimize the test time, two optimization solutions are introduced. The first solution minimizes the number of input test pins, and the second solution minimizes the number of output test pins. In addition, two subgroup configuration methods are further proposed to generate subgroups inside each test group. To highlight the effectiveness of the proposed test strategies, we present scheduling and optimization results for two SoC dies for 2.5D ICs currently in production.

Full Text

Duke Authors

Cited Authors

  • Wang, R; Li, G; Li, R; Qian, J; Chakrabarty, K

Published Date

  • January 1, 2016

Published In

Volume / Issue

  • PP / 99

International Standard Serial Number (ISSN)

  • 0278-0070

Digital Object Identifier (DOI)

  • 10.1109/TCAD.2016.2611515

Citation Source

  • Scopus