A design-for-test solution for monolithic 3D integrated circuits

Conference Paper

Monolithic three-dimensional integrated circuits (M3D ICs) are being advocated as the next generation of 3D integration beyond 3D ICs based on through-silicon-vias. Testing of the bottom layer of an M3D IC is necessary to target defects arising from the layered manufacturing process. We present an efficient design-for-test (DfT) method for the bottom layer by isolating it from the top layer. A bypass structure based on e-fuses is proposed to connect pairs of inter-layer vias (ILVs). In order to minimize the wire length between paired ILVs, an ILV-pairing problem is formulated and then solved using a technique based on maximum-weighted bipartite matching. The independent ILVs, i.e., those that are not paired, are made controllable and observable using four different types of DfT structures. A cost-optimization problem is solved to minimize the DfT cost. We present ILV-pairing and cost-optimization results for designs based on the ITC′02 benchmarks as well as for an industry design. We also present HSpice simulation results to show that testing using e-fuses is feasible.

Full Text

Duke Authors

Cited Authors

  • Wang, R; Chakrabarty, K

Published Date

  • July 22, 2016

Published In

Volume / Issue

  • 2016-July /

Electronic International Standard Serial Number (EISSN)

  • 1558-1780

International Standard Serial Number (ISSN)

  • 1530-1877

International Standard Book Number 13 (ISBN-13)

  • 9781467396592

Digital Object Identifier (DOI)

  • 10.1109/ETS.2016.7519311

Citation Source

  • Scopus