The hype, myths, and realities of testing 3D integrated circuits
© 2016 ACM. Three-dimensional (3D) integration using through-silicon vias (TSVs) promises higher integration levels in a single package, keeping pace with Moore's law. Despite the promise and benefits offered by 3D integration, testing remains a major obstacle that hinders its widespread adoption. This paper examines the hype, myths, and realities of 3D IC testing. We describe a number of testing and DfT challenges, and present some solutions being advocated for the challenges of "What to Test", "How to Test", and "When to Test". Techniques highlighted in this paper include: (i) testing of the silicon interposer; (ii) pre-bond TSV testing; (iii) cost modeling and test-flow selection; (iv) a reconfigurable built-in self-test infrastructure.
Wang, R; Deutsch, S; Agrawal, M; Chakrabarty, K
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International Standard Book Number 13 (ISBN-13)
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