The hype, myths, and realities of testing 3D integrated circuits

Published

Conference Paper

© 2016 ACM. Three-dimensional (3D) integration using through-silicon vias (TSVs) promises higher integration levels in a single package, keeping pace with Moore's law. Despite the promise and benefits offered by 3D integration, testing remains a major obstacle that hinders its widespread adoption. This paper examines the hype, myths, and realities of 3D IC testing. We describe a number of testing and DfT challenges, and present some solutions being advocated for the challenges of "What to Test", "How to Test", and "When to Test". Techniques highlighted in this paper include: (i) testing of the silicon interposer; (ii) pre-bond TSV testing; (iii) cost modeling and test-flow selection; (iv) a reconfigurable built-in self-test infrastructure.

Full Text

Duke Authors

Cited Authors

  • Wang, R; Deutsch, S; Agrawal, M; Chakrabarty, K

Published Date

  • November 7, 2016

Published In

Volume / Issue

  • 07-10-November-2016 /

International Standard Serial Number (ISSN)

  • 1092-3152

International Standard Book Number 13 (ISBN-13)

  • 9781450344661

Digital Object Identifier (DOI)

  • 10.1145/2966986.2980097

Citation Source

  • Scopus