A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations

Conference Paper

Multi-level cell spin-transfer torque random access memory (MLC STT-RAM) demonstrates great potentials in onchip cache design for its high storage density and non-volatility but also suffers from the degraded access time, reliability and energy efficiency. The existing MLC STT-RAM cache designs primarily focus on the performance and energy optimizations, however, often ignore the crucial demand for reliability. In this work, we propose a tri-region MLC STT-RAM cache design (TMSC) to simultaneously meet the requirements of performance, energy, and reliability. The tri-region MLC STT-RAM cache is optimized partitioned into fast, mixed, and slow ways according to different access performance, energy and reliability. A new error correction code (ECC) scheme, namely, non-uniform strength ECC (NUS-ECC), is also developed to tolerate the different bit failure rates in these ways. Compared to the latest performance-driven MLC STT-RAM cache design with pessimistic ECC scheme, our TMSC technique can improve the system performance and energy by averagely 9.3% and 9.4%, respectively, for various applications. The additional area cost associated with NUS-ECC is limited by 3.2% compared to the pessimistic ECC scheme.

Full Text

Duke Authors

Cited Authors

  • Wen, W; Mao, M; Li, H; Chen, Y; Pei, Y; Ge, N

Published Date

  • April 25, 2016

Published In

  • Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, Date 2016

Start / End Page

  • 1285 - 1290

International Standard Book Number 13 (ISBN-13)

  • 9783981537062

Digital Object Identifier (DOI)

  • 10.3850/9783981537079_0917

Citation Source

  • Scopus