Design exploration of racetrack lower-level caches

Conference Paper

The recent successful integration of magnetic racetrack memory forecasts a new computing era with unprecedentedly high-density on-chip storage. However, racetrack memory accesses require frequent magnetic domain shifting, introducing overheads in access latency and energy consumption. In this paper, we evaluate and compare several different physical layout strategies and array organizations. From this evaluation, a workload-oriented racetrack LLC architecture is proposed that combines different array types, each of which is tailored to a specific data access pattern. Further, a resizable cache access strategy is applied to reduce shifting overheads at runtime. Our simulation results show that compared with the leading racetrack-based cache, the proposed racetrack LLC can improve system performance by 13.2% reduce LLC energy consumption by 30.4%. Copyright 2014 ACM.

Full Text

Duke Authors

Cited Authors

  • Sun, Z; Bi, X; Jones, AK; Li, H

Published Date

  • January 1, 2014

Published In

Start / End Page

  • 263 - 266

International Standard Serial Number (ISSN)

  • 1533-4678

International Standard Book Number 13 (ISBN-13)

  • 9781450329750

Digital Object Identifier (DOI)

  • 10.1145/2627369.2627651

Citation Source

  • Scopus