Skip to main content

Identifying wafer-level systematic failure patterns via unsupervised learning

Publication ,  Journal Article
Alawieh, MB; Wang, F; Li, X
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
April 1, 2018

In this paper, we propose a novel methodology for detecting systematic failure patterns at the wafer level for yield learning. Our proposed methodology takes the binary testing results (i.e., pass or fail) of all dies over multiple wafers, cluster these wafers according to their spatial signatures of failures, and eventually identify the underlying systematic failure patterns. Several data processing techniques, including singular value decomposition, hierarchical clustering, etc., are adopted to make the proposed methodology robust to random failures. In addition, a Pseudo-Boolean satisfiability solver is used to extract a minimal set of systematic failure patterns that explain all wafer-level spatial signatures. These patterns help process engineers identify the root causes of failures and accelerate yield learning. The efficacy of our proposed approach is demonstrated by one synthetic data set and one industrial data set.

Duke Scholars

Published In

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

ISSN

0278-0070

Publication Date

April 1, 2018

Volume

37

Issue

4

Start / End Page

832 / 844

Related Subject Headings

  • Computer Hardware & Architecture
  • 4607 Graphics, augmented reality and games
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering
 

Citation

APA
Chicago
ICMJE
MLA
NLM
Alawieh, M. B., Wang, F., & Li, X. (2018). Identifying wafer-level systematic failure patterns via unsupervised learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(4), 832–844. https://doi.org/10.1109/TCAD.2017.2729469
Alawieh, M. B., F. Wang, and X. Li. “Identifying wafer-level systematic failure patterns via unsupervised learning.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, no. 4 (April 1, 2018): 832–44. https://doi.org/10.1109/TCAD.2017.2729469.
Alawieh MB, Wang F, Li X. Identifying wafer-level systematic failure patterns via unsupervised learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2018 Apr 1;37(4):832–44.
Alawieh, M. B., et al. “Identifying wafer-level systematic failure patterns via unsupervised learning.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 4, Apr. 2018, pp. 832–44. Scopus, doi:10.1109/TCAD.2017.2729469.
Alawieh MB, Wang F, Li X. Identifying wafer-level systematic failure patterns via unsupervised learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2018 Apr 1;37(4):832–844.

Published In

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

ISSN

0278-0070

Publication Date

April 1, 2018

Volume

37

Issue

4

Start / End Page

832 / 844

Related Subject Headings

  • Computer Hardware & Architecture
  • 4607 Graphics, augmented reality and games
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering