A look up table design with 3D bipolar RRAMs

Conference Paper

Look Up Table (LUT) is a basic configurable logic element in Field Programmable Gate Arrays (FPGAs). In a commercial product, Static Random Access Memory (SRAM) has been widely used in each LUT to store configured logic. Recently, emerging Resistive RAM (RRAM) has attracted a lot of attention for its high density and non-volatility. In this work, we explore a novel LUT design with bipolar RRAM devices. To obtain design efficiency, a 3D high-density interleaved memory structure is introduced in the proposed LUT. The corresponding peripheral circuits were developed with TSMC 0.18μm technology node. Compared to the traditional SRAM-based FPGA, the RRAM-based LUT demonstrates advantages such as a eliminating initialization stage, a much higher density with 56% area reduction, a bit-addressable write scheme, dynamic reconfiguration, and better flexibility in supporting various configurations. © 2012 IEEE.

Full Text

Duke Authors

Cited Authors

  • Chen, YC; Zhang, W; Li, H

Published Date

  • April 26, 2012

Published In

  • Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac

Start / End Page

  • 73 - 78

International Standard Book Number 13 (ISBN-13)

  • 9781467307727

Digital Object Identifier (DOI)

  • 10.1109/ASPDAC.2012.6165051

Citation Source

  • Scopus