Variable-latency adder (VL-adder): New arithmetic circuit design practice to overcome NBTI

Conference Paper

Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) technique for NBTI tolerance. By detecting the circuit failure on-the-fly, the proposed VL-adder can automatically shift data capturing clock edge to tolerate NBTI-induced delay degradation on critical timing paths. VL-adder operates with a fixed supply voltage and clock period, avoiding the high design and manufacturing costs incurred by existing NBTI-tolerant techniques. Compared to other related lower-power adder designs, VL-adder technique always provides better energy efficiency through the whole chip lifetime with very limited performance degradation (4.6% or less). Copyright 2007 ACM.

Full Text

Duke Authors

Cited Authors

  • Chen, Y; Li, H; Li, J; Koh, CK

Published Date

  • December 17, 2007

Published In

Start / End Page

  • 195 - 200

International Standard Serial Number (ISSN)

  • 1533-4678

International Standard Book Number 10 (ISBN-10)

  • 1595937099

International Standard Book Number 13 (ISBN-13)

  • 9781595937094

Digital Object Identifier (DOI)

  • 10.1145/1283780.1283822

Citation Source

  • Scopus