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Variable-latency adder (VL-adder): New arithmetic circuit design practice to overcome NBTI

Publication ,  Conference
Chen, Y; Li, H; Li, J; Koh, CK
Published in: Proceedings of the International Symposium on Low Power Electronics and Design
December 17, 2007

Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) technique for NBTI tolerance. By detecting the circuit failure on-the-fly, the proposed VL-adder can automatically shift data capturing clock edge to tolerate NBTI-induced delay degradation on critical timing paths. VL-adder operates with a fixed supply voltage and clock period, avoiding the high design and manufacturing costs incurred by existing NBTI-tolerant techniques. Compared to other related lower-power adder designs, VL-adder technique always provides better energy efficiency through the whole chip lifetime with very limited performance degradation (4.6% or less). Copyright 2007 ACM.

Duke Scholars

Published In

Proceedings of the International Symposium on Low Power Electronics and Design

DOI

ISSN

1533-4678

ISBN

9781595937094

Publication Date

December 17, 2007

Start / End Page

195 / 200
 

Citation

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Chen, Y., Li, H., Li, J., & Koh, C. K. (2007). Variable-latency adder (VL-adder): New arithmetic circuit design practice to overcome NBTI. In Proceedings of the International Symposium on Low Power Electronics and Design (pp. 195–200). https://doi.org/10.1145/1283780.1283822
Chen, Y., H. Li, J. Li, and C. K. Koh. “Variable-latency adder (VL-adder): New arithmetic circuit design practice to overcome NBTI.” In Proceedings of the International Symposium on Low Power Electronics and Design, 195–200, 2007. https://doi.org/10.1145/1283780.1283822.
Chen Y, Li H, Li J, Koh CK. Variable-latency adder (VL-adder): New arithmetic circuit design practice to overcome NBTI. In: Proceedings of the International Symposium on Low Power Electronics and Design. 2007. p. 195–200.
Chen, Y., et al. “Variable-latency adder (VL-adder): New arithmetic circuit design practice to overcome NBTI.” Proceedings of the International Symposium on Low Power Electronics and Design, 2007, pp. 195–200. Scopus, doi:10.1145/1283780.1283822.
Chen Y, Li H, Li J, Koh CK. Variable-latency adder (VL-adder): New arithmetic circuit design practice to overcome NBTI. Proceedings of the International Symposium on Low Power Electronics and Design. 2007. p. 195–200.

Published In

Proceedings of the International Symposium on Low Power Electronics and Design

DOI

ISSN

1533-4678

ISBN

9781595937094

Publication Date

December 17, 2007

Start / End Page

195 / 200