Skip to main content

Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches

Publication ,  Conference
Bi, X; Sun, Z; Li, H; Wu, W
Published in: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
January 1, 2012

Using the spin-transfer torque random access memory (STT-RAM) technology as lower level on-chip caches has been proposed to minimize leakage power consumption and enhance cache capacity at the scaled technologies. However, programming STT-RAM is a stochastic process due to the random thermal fluctuations. Conventional worst-case (corner) design with a fixed write pulse period cannot completely eliminate the write failures but maintain it at a low level by paying high cost in hardware complexity and system performance. In this work, we systematically study the impacts of the stochastic switching of STT-RAM on circuit and cache performance. Two probabilistic design techniques, write-verify-rewrite with adaptive period (WRAP) and verify-one-while-writing (VOW), then are proposed for performance improvement and write failure reduction. Our simulation results show that compared to the result of the conventional design using Hamming Code to correct the write failures, WRAP is write error free while reducing the cache write latency and energy consumption by 40% and 26%, respectively. When an extremely low write failure rate (i.e., 10-22) is allowed, VOW can further boost the reductions on write latency and energy to 52% and 29%, respectively. Furthermore, a hybrid STT-RAM based cache hierarchy taking advantages of probabilistic design techniques is proposed. The novel hierarchy can reduce the write failure rate of STT-RAM cache to 10-30, while improving the speed by 6.8% and saving 15% of energy consumption compared to a conventional design with Hamming Code. © 2012 ACM.

Duke Scholars

Published In

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

DOI

ISSN

1092-3152

Publication Date

January 1, 2012

Start / End Page

88 / 94
 

Citation

APA
Chicago
ICMJE
MLA
NLM
Bi, X., Sun, Z., Li, H., & Wu, W. (2012). Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD (pp. 88–94). https://doi.org/10.1145/2429384.2429401
Bi, X., Z. Sun, H. Li, and W. Wu. “Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches.” In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 88–94, 2012. https://doi.org/10.1145/2429384.2429401.
Bi X, Sun Z, Li H, Wu W. Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches. In: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2012. p. 88–94.
Bi, X., et al. “Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches.” IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 2012, pp. 88–94. Scopus, doi:10.1145/2429384.2429401.
Bi X, Sun Z, Li H, Wu W. Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2012. p. 88–94.

Published In

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

DOI

ISSN

1092-3152

Publication Date

January 1, 2012

Start / End Page

88 / 94