Variation tolerant sensing scheme of spin-transfer torque memory for yield improvement

Published

Conference Paper

Spin-Transfer Torque Random Access Memory (STTRAM) demonstrated great potentials as an universal memory for its fast access speed, zero standby power, excellent scalability and simplicity of cell structure. However, large process variations of both magnetic tunneling junction and CMOS process severely limit the yield of STT-RAM chips and prevent the massive production from happening. In this paper, we analyze the impacts of process variations on various sensing schemes of STTRAM. Based on our analysis, we propose a novel voltage-driven non-destructive self-reference sensing scheme (VDRS) to enhance the STT-RAM chip yield by significantly improving sense margin. Monte-Carlo simulations of a 16Kb STT-RAM array shows that VDRS can achieve the same yield as the previous non-destructive self-reference sensing scheme while improving the sense margin by 5.16 times with the similar access performance and power. ©2010 IEEE.

Full Text

Duke Authors

Cited Authors

  • Sun, Z; Li, H; Chen, Y; Wang, X

Published Date

  • December 1, 2010

Published In

Start / End Page

  • 432 - 437

International Standard Serial Number (ISSN)

  • 1092-3152

International Standard Book Number 13 (ISBN-13)

  • 9781424481927

Digital Object Identifier (DOI)

  • 10.1109/ICCAD.2010.5653720

Citation Source

  • Scopus