CD-ECC: Content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors


Conference Paper

The write operation asymmetry of many memory technologies causes different write failure rates at 0 →1 and 1 → 0 bit-flipping's. Conventional error correction codes (ECCs) spend the same efforts on both bit-flipping directions, leading to very unbalanced write reliability enchantment over different bit-flipping distributions of codewords (i.e., the number of 0 →1 or 1 → 0 bit-flipping's). In this work, we developed an analytic asymmetric write channel (AWC) model to analyze the asymmetric write errors in spin-transfer torque random access memory (STT-RAM) designs. A new ECC design concept, namely, content-dependent ECC (CD-ECC), is proposed to achieve balanced error correction at both bit-flipping directions. Two CD-ECC schemes - typical-corner-ECC (TCE) and worst-corner-ECC (WCE), are designed for the codewords with different bit-flipping distributions. Our simulation results show that compared to the common ECC schemes utilized in embedded applications like Hamming code, CD-ECCs can improve the STT-RAM write reliability by 10 - 30x with low hardware overhead and very marginal impact on system performance. © 2013 IEEE.

Full Text

Duke Authors

Cited Authors

  • Wen, W; Mao, M; Zhu, X; Kang, SH; Wang, D; Chen, Y

Published Date

  • December 1, 2013

Published In

Start / End Page

  • 1 - 8

International Standard Serial Number (ISSN)

  • 1092-3152

International Standard Book Number 13 (ISBN-13)

  • 9781479910717

Digital Object Identifier (DOI)

  • 10.1109/ICCAD.2013.6691090

Citation Source

  • Scopus