A novel architecture of the 3D stacked MRAM L2 Cache for CMPs

Conference Paper

Magnetic random access memory (MRAM) is a promising memory technology, which has fast read access, high density, and non-volatility. Using 3D heterogeneous integrations, it becomes feasible and cost-efficient to stack MRAM atop conventional chip multiprocessors (CMPs). However, one disadvantage of MRAM is its long write latency and its high write energy. In this paper, we first stackMRAM-based L2 caches directly atop CMPs and compare it against SRAM counterparts in terms of performance and energy. We observe that the direct MRAM stacking might harm the chip performance due to the aforementioned long write latency and high write energy. To solve this problem, we then propose two architectural techniques: read-preemptive write buffer and SRAM-MRAM hybrid L2 cache. The simulation result shows that our optimized MRAM L2 cache improves performance by 4.91% and reduces power by 73.5%compared to the conventional SRAM L2 cache with the similar area. © 2008 IEEE.

Full Text

Duke Authors

Cited Authors

  • Sun, G; Dong, X; Xie, Y; Li, J; Chen, Y

Published Date

  • January 1, 2009

Published In

Start / End Page

  • 239 - 249

International Standard Serial Number (ISSN)

  • 1530-0897

International Standard Book Number 13 (ISBN-13)

  • 9781424429325

Digital Object Identifier (DOI)

  • 10.1109/HPCA.2009.4798259

Citation Source

  • Scopus