Gated Decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies

Published

Conference Paper

A novel on-chip Decoupling Capacitor (Decap) design - Gated Decoupling Capacitor (GDecap) - is proposed to minimize the leakage power dissipation associated with present-day on-chip decoupling capacitors. Experiments on the application of GDecap in an 8-way clock-gated cluster pipeline show that on average, 41.7% Decap leakage power is improved, with only 0.037% worst-case performance degradation, at 70nm technology node. Around 5.36% area overhead in Decap area is incurred, compared to the conventional Decap deployment. © 2005 IEEE.

Full Text

Duke Authors

Cited Authors

  • Chen, Y; Li, H; Roy, K; Koh, CK

Published Date

  • December 1, 2005

Published In

Volume / Issue

  • 2005 /

Start / End Page

  • 770 - 773

International Standard Serial Number (ISSN)

  • 0886-5930

International Standard Book Number 10 (ISBN-10)

  • 0780390237

International Standard Book Number 13 (ISBN-13)

  • 9780780390232

Digital Object Identifier (DOI)

  • 10.1109/CICC.2005.1568783

Citation Source

  • Scopus