Efficient Hierarchical Performance Modeling for Integrated Circuits via Bayesian Co-Learning


Conference Paper

© 2017 ACM. With the continuous drive towards integrated circuits scaling, efficient performance modeling is becoming more crucial yet, more challenging. In this paper, we propose a novel method of hierarchical performance modeling based on Bayesian co-learning. We exploit the hierarchical structure of a circuit to establish a Bayesian framework where unlabeled data samples are generated to improve modeling accuracy without running additional simulation. Consequently, our proposed method only requires a small number of labeled samples, along with a large number of unlabeled samples obtained at almost no-cost, to accurately learn a performance model. Our numerical experiments demonstrate that the proposed approach achieves up to 3.66x runtime speed-up over the state-of-the-art modeling technique without surrendering any accuracy.

Full Text

Duke Authors

Cited Authors

  • Alawieh, M; Wang, F; Li, X

Published Date

  • June 18, 2017

Published In

Volume / Issue

  • Part 128280 /

International Standard Serial Number (ISSN)

  • 0738-100X

International Standard Book Number 13 (ISBN-13)

  • 9781450349277

Digital Object Identifier (DOI)

  • 10.1145/3061639.3062235

Citation Source

  • Scopus