Training fixed-point classifiers for on-chip low-power implementation

Journal Article (Journal Article)

In this article, we develop several novel algorithms to train classifiers that can be implemented on chip with low-power fixed-point arithmetic with extremely small word length. These algorithms are based on Linear Discriminant Analysis (LDA), Support Vector Machine (SVM), and Logistic Regression (LR), and are referred to as LDA-FP, SVM-FP, and LR-FP, respectively. They incorporate the nonidealities (i.e., rounding and overflow) associated with fixed-point arithmetic into the offline training process so that the resulting classifiers are robust to these nonidealities. Mathematically, LDA-FP, SVM-FP, and LR-FP are formulated as mixed integer programming problems that can be robustly solved by the branch-and-bound methods described in this article. Our numerical experiments demonstrate that LDA-FP, SVM-FP, and LR-FP substantially outperform the conventional approaches for the emerging biomedical applications of brain decoding.

Full Text

Duke Authors

Cited Authors

  • Albalawi, H; Li, Y; Li, X

Published Date

  • June 1, 2017

Published In

Volume / Issue

  • 22 / 4

Electronic International Standard Serial Number (EISSN)

  • 1557-7309

International Standard Serial Number (ISSN)

  • 1084-4309

Digital Object Identifier (DOI)

  • 10.1145/3057275

Citation Source

  • Scopus