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Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors

Publication ,  Journal Article
Liao, C; Tao, J; Yu, H; Tang, Z; Su, Y; Zhou, D; Zeng, X; Li, X
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
December 1, 2016

Efficient performance modeling is an extremely important task for yield analysis and design optimization of analog circuits. In this paper, a novel regression modeling method based on hierarchical shrinkage priors is proposed to construct hybrid performance models with both high accuracy and low computational cost. In particular, the user-defined model templates derived from design equations and the general-purpose orthogonal polynomials are combined together to set up a hybrid dictionary. Next, in order to avoid over-shrinking large model coefficients, a novel regression method based on hierarchical shrinkage priors and variational Bayesian inference is adopted for model fitting. A rail-to-rail operational amplifier example demonstrates that the proposed method achieves up to 40% error reduction over other state-of-the-art approaches without increasing the modeling cost.

Duke Scholars

Published In

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

ISSN

0278-0070

Publication Date

December 1, 2016

Volume

35

Issue

12

Start / End Page

2148 / 2152

Related Subject Headings

  • Computer Hardware & Architecture
  • 4607 Graphics, augmented reality and games
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering
 

Citation

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MLA
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Liao, C., Tao, J., Yu, H., Tang, Z., Su, Y., Zhou, D., … Li, X. (2016). Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35(12), 2148–2152. https://doi.org/10.1109/TCAD.2016.2543021
Liao, C., J. Tao, H. Yu, Z. Tang, Y. Su, D. Zhou, X. Zeng, and X. Li. “Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, no. 12 (December 1, 2016): 2148–52. https://doi.org/10.1109/TCAD.2016.2543021.
Liao C, Tao J, Yu H, Tang Z, Su Y, Zhou D, et al. Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2016 Dec 1;35(12):2148–52.
Liao, C., et al. “Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 12, Dec. 2016, pp. 2148–52. Scopus, doi:10.1109/TCAD.2016.2543021.
Liao C, Tao J, Yu H, Tang Z, Su Y, Zhou D, Zeng X, Li X. Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2016 Dec 1;35(12):2148–2152.

Published In

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI

ISSN

0278-0070

Publication Date

December 1, 2016

Volume

35

Issue

12

Start / End Page

2148 / 2152

Related Subject Headings

  • Computer Hardware & Architecture
  • 4607 Graphics, augmented reality and games
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering