Low-power hardware implementation of movement decoding for brain computer interface with reduced-resolution discrete cosine transform.

Published

Conference Paper

This paper describes a low-power hardware implementation for movement decoding of brain computer interface. Our proposed hardware design is facilitated by two novel ideas: (i) an efficient feature extraction method based on reduced-resolution discrete cosine transform (DCT), and (ii) a new hardware architecture of dual look-up table to perform discrete cosine transform without explicit multiplication. The proposed hardware implementation has been validated for movement decoding of electrocorticography (ECoG) signal by using a Xilinx FPGA Zynq-7000 board. It achieves more than 56× energy reduction over a reference design using band-pass filters for feature extraction.

Full Text

Duke Authors

Cited Authors

  • Minho Won, ; Albalawi, H; Xin Li, ; Thomas, DE

Published Date

  • January 2014

Published In

Volume / Issue

  • 2014 /

Start / End Page

  • 1626 - 1629

PubMed ID

  • 25570284

Pubmed Central ID

  • 25570284

International Standard Serial Number (ISSN)

  • 1557-170X

Digital Object Identifier (DOI)

  • 10.1109/embc.2014.6943916