Efficient parametric yield estimation of analog/mixed-signal circuits via Bayesian model fusion


Conference Paper

Parametric yield estimation is one of the most critical-yet-challenging tasks for designing and verifying nanoscale analog and mixed-signal circuits. In this paper, we propose a novel Bayesian model fusion (BMF) technique for efficient parametric yield estimation. Our key idea is to borrow the simulation data from an early stage (e.g., schematic-level simulation) to efficiently estimate the performance distributions at a late stage (e.g., post-layout simulation). BMF statistically models the correlation between early-stage and late-stage performance distributions by Bayesian inference. In addition, a convex optimization is formulated to solve the unknown late-stage performance distributions both accurately and robustly. Several circuit examples designed in a commercial 32 nm CMOS process demonstrate that the proposed BMF technique achieves up to 3.75× runtime speedup over the traditional kernel estimation method. © 2012 ACM.

Full Text

Duke Authors

Cited Authors

  • Li, X; Zhang, W; Wang, F; Sun, S; Gu, C

Published Date

  • January 1, 2012

Published In

Start / End Page

  • 627 - 634

International Standard Serial Number (ISSN)

  • 1092-3152

Digital Object Identifier (DOI)

  • 10.1145/2429384.2429519

Citation Source

  • Scopus