Active on-die suppression of power supply noise

Conference Paper

An active on-chip circuit is demonstrated in 130nm CMOS for the suppression of on-chip power supply noise due to power distribution resonance. Testchip measurement results indicate up to 40% reduction in power supply noise during clock/power gating at a 2% power and 6% area overhead cost. Oscillation time is reduced by 50%. Simulation results show that comparable overshoot/undershoot and ringing control via onchip decoupling would require significantly more area and power due to leakage, particularly at 90nm and below. © 2006 IEEE.

Full Text

Duke Authors

Cited Authors

  • Keskin, G; Li, X; Pileggi, L

Published Date

  • December 1, 2006

Published In

Start / End Page

  • 813 - 816

International Standard Serial Number (ISSN)

  • 0886-5930

International Standard Book Number 10 (ISBN-10)

  • 1424400767

International Standard Book Number 13 (ISBN-13)

  • 9781424400768

Digital Object Identifier (DOI)

  • 10.1109/CICC.2006.321012

Citation Source

  • Scopus