Performance-centering optimization for system-level analog design exploration

Conference Paper

In this paper we propose a novel analog design optimization methodology to address two key aspects of top-down system-level design: (1) how to optimally compare and select analog system architectures in the early phases of design; and (2) how to hierarchically propagate performance specifications from system level to circuit level to enable independent circuit block design. Importantly, due to the inaccuracy of early-stage system-level models, and the increasing magnitude of process and environmental variations, the system-level exploration must leave sufficient design margin to ensure a successful late-stage implementation. Therefore, instead of minimizing a design objective function, and thereby converging on a constraint boundary, we apply a novel performance centering optimization. Our proposed methodology centers the analog design in the performance space, and maximizes the distance to all constraint boundaries. We demonstrate that this early-stage design margin, which is measured by the volume of the inscribed ellipsoid lying inside the performance constraints, provides an excellent quality measure for comparing different system architectures. The efficacy of our performance centering approach is shown for analog design examples, including a complete clock data recovery system design and implementation. © 2005 IEEE.

Full Text

Duke Authors

Cited Authors

  • Li, X; Wang, J; Pileggi, LT; Chen, TS; Chiang, W

Published Date

  • January 1, 2005

Published In

Volume / Issue

  • 2005 /

Start / End Page

  • 422 - 429

International Standard Serial Number (ISSN)

  • 1092-3152

International Standard Book Number 10 (ISBN-10)

  • 078039254X

International Standard Book Number 13 (ISBN-13)

  • 9780780392540

Digital Object Identifier (DOI)

  • 10.1109/ICCAD.2005.1560105

Citation Source

  • Scopus