Efficient statistical analysis of read timing failures in sram circuits

Conference Paper

A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. Unlike existing approaches that focus on cell-level performance metrics for isolated sub-components or ignore inter-die variability, the system-level performance is accurately predicted for the entire SRAM circuit that is impractical to analyze statistically via transistor-level Monte Carlo simulations. The accurate bounding of read timing failures using this methodology is validated with silicon measurements from a 64kb SRAM testchip in 90nm CMOS. We demonstrate the efficacy of this methodology for earlystage design exploration to specify redundancy, required sense amp offset, and other circuit choices as a function of memory size. © 2009 IEEE.

Full Text

Duke Authors

Cited Authors

  • Yaldiz, S; Arslan, U; Li, X; Pileggi, L

Published Date

  • July 8, 2009

Published In

  • Proceedings of the 10th International Symposium on Quality Electronic Design, Isqed 2009

Start / End Page

  • 617 - 621

International Standard Book Number 13 (ISBN-13)

  • 9781424429530

Digital Object Identifier (DOI)

  • 10.1109/ISQED.2009.4810365

Citation Source

  • Scopus