Digital circuit design challenges and opportunities in the era of nanoscale CMOS


Journal Article

Well-designed circuits are one key ldquoinsulatingrdquo layer between the increasingly unruly behavior of scaled complementary metal-oxide-semiconductor devices and the systems we seek to construct from them. As we move forward into the nanoscale regime, circuit design is burdened to ldquohiderdquo more of the problems intrinsic to deeply scaled devices. How this is being accomplished is the subject of this paper. We discuss new techniques for logic circuits and interconnect, for memory, and for clock and power distribution. We survey work to build accurate simulation models for nanoscale devices. We discuss the unique problems posed by nanoscale lithography and the role of geometrically regular circuits as one promising solution. Finally, we look at recent computer-aided design efforts in modeling, analysis, and optimization for nanoscale designs with ever increasing amounts of statistical variation. © 2008 IEEE.

Full Text

Duke Authors

Cited Authors

  • Calhoun, BH; Cao, Y; Li, X; Mai, K; Pileggi, LT; Rutenbar, RA; Shepard, KL

Published Date

  • January 1, 2008

Published In

Volume / Issue

  • 96 / 2

Start / End Page

  • 343 - 365

International Standard Serial Number (ISSN)

  • 0018-9219

Digital Object Identifier (DOI)

  • 10.1109/JPROC.2007.911072

Citation Source

  • Scopus