Mismatch analysis and statistical design at 65 nm and below

Published

Conference Paper

Transistor sizing to control random mismatch is investigated. Input offset voltage of 65nm bulk CMOS SRAM sense amplifiers are measured to analyze NMOS and PMOS threshold voltage (Vtn, Vtp) variation effects and compare them with statistical models and Pelgrom model predictions. A linear statistical response surface model (RSM) relating input offset to Vtn and Vtp is shown to agree well with measured results. Designs optimized using the RSMs produce circuits with 25% lower input offset voltage spread at a cost of 10% more active device area. Statistical models for post-manufacturing configuration are postulated and shown for sub-65nm technologies. © 2008 IEEE.

Full Text

Duke Authors

Cited Authors

  • Pileggi, L; Keskin, G; Li, X; Mai, K; Proesel, J

Published Date

  • December 26, 2008

Published In

Start / End Page

  • 9 - 12

International Standard Serial Number (ISSN)

  • 0886-5930

Digital Object Identifier (DOI)

  • 10.1109/CICC.2008.4672006

Citation Source

  • Scopus