Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines

Published

Conference Paper

A configurable replica bitline (cRBL) technique for controlling sense-amplifier enable (SAE) timing for small-swing bitline SRAMs is described. Post-silicon selection of a subset of replica bitline driver cells from a statistically designed pool of cells facilitates precise SAE timing. An exponential reduction in timing variation is enabled by statistical selection of driver cells, which can provide 14x reduction in SAE timing uncertainty with 200x less area and power than a conventional RBL with equivalent variation control. We describe the post-silicon test and configuration methodology necessary for cRBLs. To demonstrate the efficacy of the proposed cRBL technique, we present measured results from a 90nm bulk CMOS 64kb SRAM testchip. ©2008 IEEE.

Full Text

Duke Authors

Cited Authors

  • Arslan, U; McCartney, MP; Bhargava, M; Li, X; Mai, K; Pileggi, LT

Published Date

  • December 26, 2008

Published In

Start / End Page

  • 415 - 418

International Standard Serial Number (ISSN)

  • 0886-5930

Digital Object Identifier (DOI)

  • 10.1109/CICC.2008.4672108

Citation Source

  • Scopus