Testing 3D-SoCs using 2-D time-division multiplexing

Published

Journal Article

© 1982-2012 IEEE. Through-silicon vias (TSVs) are used as high-speed vertical interconnects between dies in a 3-D system-on-a-chip (SoC). However, their speed cannot be exploited during test application due to inherent limitations of the scan-chains of the cores, which prevent the use of high shift frequencies during the scan-in/out operations. Moreover, due to their high area cost, only a limited number of TSVs can be utilized for test application. As a result, TSVs become the bottleneck for transferring the large volume of test-data to the various layers of the stack, and the time for testing the 3-D chip increases a lot. In this paper, we propose an efficient test-access mechanism (TAM) architecture that exploits the high speed of TSVs to minimize the time for testing 3-D SoCs. The proposed TAM architecture is based on a 2-D time-division-multiplexing approach, and by the means of a very effective test-scheduling method, it offers significant savings in test-time, TSV-count and TAM-cost under power and thermal constraints. Extensive experiments on two 3-D benchmark SoCs show the benefits of the proposed method.

Full Text

Duke Authors

Cited Authors

  • Georgiou, P; Vartziotis, F; Kavousianos, X; Chakrabarty, K

Published Date

  • December 1, 2018

Published In

Volume / Issue

  • 37 / 12

Start / End Page

  • 3177 - 3185

International Standard Serial Number (ISSN)

  • 0278-0070

Digital Object Identifier (DOI)

  • 10.1109/TCAD.2017.2780054

Citation Source

  • Scopus