Online soft-error vulnerability estimation for memory arrays and logic cores

Published

Journal Article

© 2017 IEEE. Radiation-induced soft errors are a major reliability concern in circuits fabricated at advanced technology nodes. Online soft-error vulnerability estimation offers the flexibility of exploiting dynamic fault-tolerant mechanisms for cost-effective reliability enhancement. We propose a generic run-time method with low area and power overhead to predict the soft-error vulnerability of on-chip memory arrays as well as logic cores. The vulnerability prediction is based on signal probabilities (SPs) of a small set of flip-flops, chosen at design time, by studying the correlation between the soft-error vulnerability and the flip-flop SPs for representative workloads. We exploit machine learning to develop a predictive model that can be deployed in the system in software form. Simulation results on two processor designs show that the proposed technique can accurately estimate the soft-error vulnerability of on-chip logic core, such as sequential pipeline logic and functional units as well as memory arrays that constitute the instruction cache, the data cache, and the register file.

Full Text

Duke Authors

Cited Authors

  • Vijayan, A; Kiamehr, S; Ebrahimi, M; Chakrabarty, K; Tahoori, MB

Published Date

  • February 1, 2018

Published In

Volume / Issue

  • 37 / 2

Start / End Page

  • 499 - 511

International Standard Serial Number (ISSN)

  • 0278-0070

Digital Object Identifier (DOI)

  • 10.1109/TCAD.2017.2706558

Citation Source

  • Scopus