An introduction to an array memory processor for application specific acceleration

Published

Conference Paper

© 2017 IEEE. In this paper, we introduce an Array Memory (AM) processor. The AM processor uses a shared memory network amenable to on-chip 3D stacking. Node couplings use a 1 to K adjacency of connections in each dimension of communication of an array of nodes, such as an R×C array where R ≥ K and C ≥ K and K is a positive odd integer. This design also provides data sharing between processors within sub-arrays of the R × C array to support high-performance programmable application specific processing. A new instruction set architecture is proposed that has arithmetic instructions that do not require the specification of any source or target operand addresses. The source operands and target values are provided by separate load, store, and arithmetic instructions that are appropriately scheduled with the arithmetic instruction to be executed to reduce the storage of temporary variables for lower power implementations.

Full Text

Duke Authors

Cited Authors

  • Pechanek, GG; Pitsianis, N

Published Date

  • October 30, 2017

Published In

  • 2017 Ieee High Performance Extreme Computing Conference, Hpec 2017

International Standard Book Number 13 (ISBN-13)

  • 9781538634721

Digital Object Identifier (DOI)

  • 10.1109/HPEC.2017.8091069

Citation Source

  • Scopus