Jenga: Efficient fault tolerance for stacked DRAM
© 2017 IEEE. In this paper, we introduce Jenga, a new scheme for protecting 3D DRAM, specifically high bandwidth memory (HBM), from failures in bits, rows, banks, channels, dies, and TSVs. By providing redundancy at the granularity of a cache block rather than across blocks, as in the current state of the art Jenga achieves greater error-free performance and lower error recovery latency. We show that Jenga's runtime is on average only 1.03 the runtime of our Baseline across a range of benchmarks. Additionally, for memory intensive benchmarks, Jenga is on average 1.11 faster than prior work.
Mappouras, G; Vahid, A; Calderbank, R; Hower, DR; Sorin, DJ
Proceedings 35th Ieee International Conference on Computer Design, Iccd 2017
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International Standard Book Number 13 (ISBN-13)
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