Jenga: Efficient fault tolerance for stacked DRAM

Conference Paper

© 2017 IEEE. In this paper, we introduce Jenga, a new scheme for protecting 3D DRAM, specifically high bandwidth memory (HBM), from failures in bits, rows, banks, channels, dies, and TSVs. By providing redundancy at the granularity of a cache block rather than across blocks, as in the current state of the art Jenga achieves greater error-free performance and lower error recovery latency. We show that Jenga's runtime is on average only 1.03 the runtime of our Baseline across a range of benchmarks. Additionally, for memory intensive benchmarks, Jenga is on average 1.11 faster than prior work.

Full Text

Duke Authors

Cited Authors

  • Mappouras, G; Vahid, A; Calderbank, R; Hower, DR; Sorin, DJ

Published Date

  • November 22, 2017

Published In

  • Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017

Start / End Page

  • 361 - 368

International Standard Book Number 13 (ISBN-13)

  • 9781538622544

Digital Object Identifier (DOI)

  • 10.1109/ICCD.2017.62

Citation Source

  • Scopus