Design automation and testing of monolithic 3D ICs: Opportunities, challenges, and solutions: (Invited paper)

Published

Conference Paper

© 2017 IEEE. Monolithic 3D ICs (M3D) are fabricated using a sequential process that grows new device and interconnect tiers in a bottom-up fashion. This fabrication process is in contrast to through-silicon via (TSV) technology that aligns and bonds pre-built tiers. M3D offers key advantages over TSVs, including (1) orders-of-magnitude smaller inter-tier vias, (2) no need for high alignment accuracy, (3) finer-grained tier partitioning options, etc. Recent studies have shown power, performance, area, and reliability (PPAR) advantages of M3D over TSV. However, M3D also suffers from its own problems, including (1) device and interconnect performance mismatch between tiers, (2) lack of EDA solutions, (3) testing challenges, (4) cost, etc. Research efforts have also been made to model and mitigate the impact of these undesirable characteristics of M3D. We will provide a survey of work that address the above issues and conclude with future directions.

Full Text

Duke Authors

Cited Authors

  • Chang, K; Koneru, A; Chakrabarty, K; Lim, SK

Published Date

  • December 13, 2017

Published In

Volume / Issue

  • 2017-November /

Start / End Page

  • 805 - 810

International Standard Serial Number (ISSN)

  • 1092-3152

International Standard Book Number 13 (ISBN-13)

  • 9781538630938

Digital Object Identifier (DOI)

  • 10.1109/ICCAD.2017.8203860

Citation Source

  • Scopus