A design-for-test solution for monolithic 3D integrated circuits

Conference Paper

Monolithic three-dimensional (M3D) integration has the potential to achieve significantly higher device density compared to 3D integration based on through-silicon vias (TSVs). We propose a test solution for M3D ICs based on dedicated test layers that are inserted between functional layers. We evaluate the cost associated with the proposed design-for-test (DfT) solution and compare it with that for a potential DfT solution based on the IEEE Std. P1838. Our results show that the proposed solution is more cost-efficient than the P1838-based solution for a wide range of inter-layer via (ILV) density, ILV yield, and defect density.

Full Text

Duke Authors

Cited Authors

  • Koneru, A; Kannan, S; Chakrabarty, K

Published Date

  • November 22, 2017

Published In

  • Proceedings 35th Ieee International Conference on Computer Design, Iccd 2017

Start / End Page

  • 685 - 688

International Standard Book Number 13 (ISBN-13)

  • 9781538622544

Digital Object Identifier (DOI)

  • 10.1109/ICCD.2017.119

Citation Source

  • Scopus