Efficient hierarchical performance modeling for analog and mixed-signal circuits via Bayesian co-learning

Published

Journal Article

© 1982-2012 IEEE. With the continuous drive toward integrated circuits scaling, efficient performance modeling is becoming more crucial yet more challenging. In this paper, we propose a novel method of hierarchical performance modeling based on Bayesian co-learning. We exploit the hierarchical structure of a circuit to establish a Bayesian framework where unlabeled data samples are generated to improve modeling accuracy without running additional simulation. Consequently, our proposed method only requires a small number of labeled samples, along with a large number of unlabeled samples obtained at almost no-cost, to accurately learn a performance model. Our numerical experiments demonstrate that the proposed approach achieves up to 3.6 × runtime speed-up over the state-of-the-art modeling technique without surrendering any accuracy.

Full Text

Duke Authors

Cited Authors

  • Alawieh, MB; Wang, F; Li, X

Published Date

  • December 1, 2018

Published In

Volume / Issue

  • 37 / 12

Start / End Page

  • 2986 - 2998

International Standard Serial Number (ISSN)

  • 0278-0070

Digital Object Identifier (DOI)

  • 10.1109/TCAD.2018.2789778

Citation Source

  • Scopus