MAPS: Understanding Metadata Access Patterns in Secure Memory

Published

Conference Paper

© 2018 IEEE. Secure memory increases both the latency and energy required for memory accesses. To reduce these overheads, computer architects have sought to cache metadata on the processor chip, but placing metadata in a simple cache has not been as effective as expected. With a detailed analysis of metadata access patterns, we clarify myths in metadata caching and provide insight into more efficient caching strategies. We provide three observations that can help architects design future metadata caches. First, caching all metadata types improves efficiency. Second, the size of the metadata cache should match the reuse distance of the metadata. Third, when designing a better eviction policy, the traditional Belady's MIN algorithm cannot be used as the optimal replacement policy.

Full Text

Duke Authors

Cited Authors

  • Lehman, TS; Hilton, AD; Lee, BC

Published Date

  • May 25, 2018

Published In

  • Proceedings 2018 Ieee International Symposium on Performance Analysis of Systems and Software, Ispass 2018

Start / End Page

  • 33 - 43

International Standard Book Number 13 (ISBN-13)

  • 9781538650103

Digital Object Identifier (DOI)

  • 10.1109/ISPASS.2018.00012

Citation Source

  • Scopus