Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation

Published

Journal Article

© 1982-2012 IEEE. In this paper, a graph-constrained sparse performance modeling method is proposed for analog circuit optimization. It builds sparse polynomial models constrained by an acyclic graph. These models can be used to solve analog optimization problems within local design spaces by using convex semidefinite programming relaxation both efficiently and robustly. Our numerical examples demonstrate that the proposed modeling and optimization method can quickly and accurately converge to a superior solution for analog circuits while the conventional method fails to work.

Full Text

Duke Authors

Cited Authors

  • Tao, J; Su, Y; Zhou, D; Zeng, X; Li, X

Published Date

  • August 1, 2019

Published In

Volume / Issue

  • 38 / 8

Start / End Page

  • 1385 - 1398

Electronic International Standard Serial Number (EISSN)

  • 1937-4151

International Standard Serial Number (ISSN)

  • 0278-0070

Digital Object Identifier (DOI)

  • 10.1109/TCAD.2018.2848590

Citation Source

  • Scopus