Defect Clustering-Aware Spare-TSV Allocation in 3-D ICs for Yield Enhancement


Journal Article

© 1982-2012 IEEE. The manufacturing yield challenge of 3-D integrated circuit is one of the key obstacles in the industry adoption of 3-D integration based on through-silicon-vias (TSVs). The addition of spare TSVs to repair faulty functional TSVs (f-TSVs) is an effective method for yield and reliability enhancement, but this approach results in significant hardware cost and delay overhead. Most existing solutions are only suitable for a 'dual-uniform' scenario in which both the placement and the defect probabilities of f-TSVs are assumed to be uniform. In this paper, we propose a design technique that is compatible with nonuniform TSV placement and it can repair faulty TSVs based on a realistic clustered defect-distribution model. The proposed solution is based on two consecutive stages, which utilize a greedy algorithm and an integer-linear-programming formulation, respectively. By considering the tradeoff between chip yield, hardware cost, and delay overhead, the proposed technique provides higher yield and reliability under a clustered defect distribution, and with minimum hardware cost and delay overhead, compared to the previous work.

Full Text

Cited Authors

  • Wang, S; Chakrabarty, K; Tahoori, MB

Published Date

  • October 1, 2019

Published In

Volume / Issue

  • 38 / 10

Start / End Page

  • 1928 - 1941

Electronic International Standard Serial Number (EISSN)

  • 1937-4151

International Standard Serial Number (ISSN)

  • 0278-0070

Digital Object Identifier (DOI)

  • 10.1109/TCAD.2018.2864291

Citation Source

  • Scopus