Design and Data Management for Magnetic Racetrack Memory

Conference Paper

Benefiting from its ultra-high storage density, high energy efficiency, and non-volatility, racetrack memory demonstrates great potential in replacing conventional SRAM as large on-chip memory. Integrating the tape-like racetrack memory, however, faces unique design challenges from cell structure to architecture design. This paper reviews some cross-layer design methodologies for racetrack memory as on-chip cache hierarchy. Research studies show that with proper architectural design and data management, racetrack memory can achieve significant area reduction, system performance enhancement, and energy saving compared to state-of-the-art memory technologies.

Full Text

Duke Authors

Cited Authors

  • Li, B; Chen, F; Kang, W; Zhao, W; Chen, Y; Li, H

Published Date

  • April 26, 2018

Published In

Volume / Issue

  • 2018-May /

International Standard Serial Number (ISSN)

  • 0271-4310

International Standard Book Number 13 (ISBN-13)

  • 9781538648810

Digital Object Identifier (DOI)

  • 10.1109/ISCAS.2018.8351681

Citation Source

  • Scopus